> -----Original Message-----
> From: [email protected] [mailto:linux-omap-
> [email protected]] On Behalf Of Y, Kishore
> Sent: Sunday, April 25, 2010 4:42 PM
> To: Tomi Valkeinen
> Cc: [email protected]
> Subject: [PATCH] OMAP3630:DSS: Updating MAX divider value
>
>
> In DPLL4 M3, M4, M5 and M6 field width has been increased by 1 bit in 3630.
> So the max divider value that can be achived will be 32 and not 16.
> In 3630 the functional clock is x1 of DPLL4 and not x2 .Hence multiplier 2
> is removed.
>
> Signed-off-by: Sudeep Basavaraj <[email protected]>
> Signed-off-by: Kishore Y <[email protected]>
> ---
> drivers/video/omap2/dss/dss.c | 28 ++++++++++++++++++++++------
> 1 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
> index 5434418..e78b67d 100644
> --- a/drivers/video/omap2/dss/dss.c
> +++ b/drivers/video/omap2/dss/dss.c
> @@ -34,8 +34,12 @@
> #include "dss.h"
>
> #define DSS_BASE 0x48050000
> -
> #define DSS_SZ_REGS SZ_512
> +#if defined(CONFIG_MACH_OMAP_ZOOM3) || defined(CONFIG_MACH_OMAP_3630SDP)
> +#define FCK_MAX_DIV 32
> +#else
> +#define FCK_MAX_DIV 16
> +#endif
>
[Hiremath, Vaibhav] This is not only applicable for ZOOM or SDP platform also
applicable for OMAP3EVM (based on AM/DM3730). And also this divider value is
not specific to board so you can not use this.
> struct dss_reg {
> u16 idx;
> @@ -223,7 +227,13 @@ void dss_dump_clocks(struct seq_file *s)
>
> seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
>
> - seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
> + if (cpu_is_omap3630())
> + seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n",
> + dpll4_ck_rate,
> + dpll4_ck_rate / dpll4_m4_ck_rate,
> + dss_clk_get_rate(DSS_CLK_FCK1));
> + else
> + seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
> dpll4_ck_rate,
> dpll4_ck_rate / dpll4_m4_ck_rate,
> dss_clk_get_rate(DSS_CLK_FCK1));
> @@ -293,7 +303,7 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
> {
> unsigned long prate;
>
> - if (cinfo->fck_div > 16 || cinfo->fck_div == 0)
> + if (cinfo->fck_div > FCK_MAX_DIV || cinfo->fck_div == 0)
[Hiremath, Vaibhav] Why don't you make use of cpu_is_omap3630() here something
like,
if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || cinfo->fck_div == 0)
> return -EINVAL;
>
> prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
> @@ -329,7 +339,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
> if (cpu_is_omap34xx()) {
> unsigned long prate;
> prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
> - cinfo->fck_div = prate / (cinfo->fck / 2);
> + if (cpu_is_omap3630())
> + cinfo->fck_div = prate / (cinfo->fck);
> + else
> + cinfo->fck_div = prate / (cinfo->fck / 2);
> } else {
> cinfo->fck_div = 0;
> }
> @@ -402,10 +415,13 @@ retry:
>
> goto found;
> } else if (cpu_is_omap34xx()) {
> - for (fck_div = 16; fck_div > 0; --fck_div) {
> + for (fck_div = FCK_MAX_DIV; fck_div > 0; --fck_div) {
[Hiremath, Vaibhav] ditto here.
Thanks,
Vaibhav
> struct dispc_clock_info cur_dispc;
>
> - fck = prate / fck_div * 2;
> + if (cpu_is_omap3630())
> + fck = prate / fck_div;
> + else
> + fck = prate / fck_div * 2;
>
> if (fck > DISPC_MAX_FCK)
> continue;
> --
> 1.5.6.3
>
>
> Regards,
> Kishore Y
> --
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