In the ARM Cortex-A9 TRM, I found a note in chapter 6.1 Note: You must invalidate the instruction cache, the data cache, and BTAC before using them. You are not required to invalidate the main TLB, even though it is recommended for safety reasons. This ensures compatibility with future revisions of the processor.
But the kernel does.. ( __v7_setup in proc-v7.S ) clean & invalidate before turning on the MMU, not just 'invalidate'. If dcache tag&data ram has garbage data when power up, I think some dirty data lines can be flushed into to L2 or L3 memory because kernel does clean. And It can pollute the memory. Is it possible in cortex-A9? Thanks.. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
