Hi Felipe, On Wed, Aug 18, 2010 at 10:16:19AM +0300, Felipe Balbi wrote: > Hi, > > On Wed, Aug 18, 2010 at 09:10:22AM +0200, Balbi Felipe (Nokia-MS/Helsinki) > wrote: > >On Wed, Aug 18, 2010 at 09:03:44AM +0200, ext Gopinath, Thara wrote: > >>>>No I am not talking about the key values. I was talking about the > >>>>register offset > >>>>for TWL4030_PM_MASTER_PROTECT_KEY. My question is, is it ok for it to be > >>>>0xd or 0xe. > >>>>Earlier we were using 0xd and in the new implementation it has been > >>>>changed to 0xe. > >> > >>Typo. Earlier we were using 0xe and in the new implementation it has > >>been changed to 0xd. > > > >you're right, I'm not sure how I came up with that value since the TRM > >shows 0x0e, maybe a copy&paste error. Will change patch 1. > > ok, it's because there's no register 0x0a. And I missed that when > defined the register space. Good catch, thanks. Should I expect a new patch then ?
Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
