Paul, > -----Original Message----- > From: Paul Walmsley [mailto:p...@pwsan.com] > Sent: Thursday, September 16, 2010 3:05 AM > To: Reddy, Teerth > Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath > Subject: RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall > in > SDRC after a Warm-reset > > Teerth, Vishwa, > > On Tue, 25 May 2010, Reddy, Teerth wrote: > > > > -----Original Message----- > > > From: Paul Walmsley [mailto:p...@pwsan.com] > > > Sent: Wednesday, May 19, 2010 6:03 AM > > > To: Reddy, Teerth > > > Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath > > > Subject: Re: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR > > > stall in SDRC after a Warm-reset > > > > > > On Fri, 23 Apr 2010, Reddy, Teerth wrote: > > > > > > > From: Teerth Reddy <tee...@ti.com> > > > > > > > > This patch has the workaround for errata 1.176. > > What's the current status of this patch? Still waiting for an updated > version. We have realized that this errata is not applicable if reset is triggered via dpll3 reset. The rootcasuse of the issues was that incase of warm reset, SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Hence the workaround was proposed. However, incase of dpll3 reset, sdrc also gets reset. In omap_prcm_arch_reset, system reset is triggered via dpll3 reset, so this WA is not applicable.
Regards Vishwa > > > - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
