* Tony Lindgren <[email protected]> [101118 09:42]:
> * Nishanth Menon <[email protected]> [101118 08:46]:
> > 
> > But after wfi in wait_sdrc_ok as part of the code executing in SRAM
> > today omap34xx_cpu_suspend -> we are waiting for DPLL3 lock prior to
> > accessing DDR -> how do we execute that logic in SDRAM?
> 
> I too am a bit concerned how this will all keep working. For light
> testing it may be running OK if it happens to run from cache..

This in the retention case, in off-idle those should be powered down..

Tony
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