In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div) field. The lcd_div is common, for deciding the DISPC core functional clock frequency, and the final pixel clock frequency for LCD display.
In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR. The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core functional clock configuration. For pixel clock configuration of primary and secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used respectively Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Raghuveer Murthy <[email protected]> --- drivers/video/omap2/dss/dss_features.c | 2 +- drivers/video/omap2/dss/dss_features.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index 4630f0c..39864f6 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -191,7 +191,7 @@ static struct omap_dss_features omap4_dss_features = { .has_feature = FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | FEAT_MGR_LCD2 | FEAT_VAR_DPLL_FCK | - FEAT_DPLL_FCK_32_DIV, + FEAT_DPLL_FCK_32_DIV | FEAT_CORE_CLK_DIV, .num_mgrs = 3, .num_ovls = 3, diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 76b5fce..ed5c880 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -37,6 +37,8 @@ enum dss_feat_id { FEAT_VAR_DPLL_FCK = 1 << 9, /* Variable DPLL Func CLK */ /* DPLL FCLK has max divider value 32 */ FEAT_DPLL_FCK_32_DIV = 1 << 10, + /* Independent core clk divider */ + FEAT_CORE_CLK_DIV = 1 << 11, }; /* DSS register field id */ -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
