Spot-checking this...
On Fri, 25 Mar 2011, Hemant Pedanekar wrote:
> +static struct clk uart1_fck = {
> + .name = "uart1_fck",
> + .parent = &sysclk10_ck,
> + .ops = &clkops_omap2_dflt,
> + .enable_reg = TI816X_CM_ALWON_UART_0_CLKCTRL,
> + .enable_bit = TI816X_MODULEMODE_SWCTRL,
> + .clkdm_name = "alwon_l3_slow_clkdm",
> + .recalc = &followparent_recalc,
> +};
Is this really in the alwon_l3_slow_clkdm clockdomain? Looking at SPRS680
section 5.2 "L4 Interconnect", these UARTs seem to be in some L4
clockdomain?
- Paul
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