On 1 September 2011 13:49, Russell King - ARM Linux <[email protected]> wrote: > Add a dsb after the isb to ensure that the previous writes to the > CP15 registers take effect before we enable the MMU. > > Signed-off-by: Russell King <[email protected]> > --- > arch/arm/mm/proc-v7.S | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S > index dec72ee..a773f4e 100644 > --- a/arch/arm/mm/proc-v7.S > +++ b/arch/arm/mm/proc-v7.S > @@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume) > mcr p15, 0, r4, c10, c2, 0 @ write PRRR > mcr p15, 0, r5, c10, c2, 1 @ write NMRR > isb > + dsb
Isn't an ISB enough here? We usually have the DSB for some background operations like cache maintenance. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
