On Fri, 16 Sep 2011, Jon Hunter wrote: > From: Jon Hunter <[email protected]> > > The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the > parent clock of the AESS_FCLK is the ABE_FCLK... > > ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK > > The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which > determine their operational frequency. However, the dividers for > the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, > which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to > 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. > Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 > and the OCP_ABE_ICLK is 1. > > The above relationship between the AESS_FCLK and OCP_ABE_ICLK > dividers ensure that the OCP_ABE_ICLK clock is always half the > frequency of the ABE_CLK... > > OCP_ABE_ICLK = ABE_FCLK/2 > > The divider for the OCP_ABE_ICLK is currently missing so add a > divider that will ensure the OCP_ABE_ICLK frequency is always half > the ABE_FCLK frequency. > > Signed-off-by: Jon Hunter <[email protected]>
Thanks, queued for 3.2. - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
