Re: Help with clk API

[Felipe Balbi]

Hi,

On Tue, Nov 15, 2011 at 06:45:17AM -0700, Paul Walmsley wrote:
> Hi Felipe
> 
> On Fri, 11 Nov 2011, Felipe Balbi wrote:
> 
> > I have a doubt about using clk API to change CLKSEL_UTMI_P1 bit for a
> > silicon errata (OMAP4460 i693) implementation.
> > 
> > According to errata, I need to switch from external to internal clock
> > during USB port suspend, wait 1ms and switch back from internal to
> > external.
> > 
> > How can I do that with clk API ? Is it by changing clk parent ? Any tips
> > would be helpful ;-) thanks
> 
> clk_set_parent() is the way to go.  There are 44xx struct clks that 
> references CLKSEL_UTMI_P1 and CLKSEL_UTMI_P2: see utmi_p1_gfclk and 
> utmi_p2_gfclk in mach-omap2/clock44xx_data.c.  The possible parent clocks 
> are listed in utmi_p1_gfclk_sel and utmi_p2_gfclk_sel in the same file.
> 
> So you should be able to clk_get() the possible parent clocks and 
> utmi_p1_gfclk during module init, then use clk_set_parent() to switch 
> between them.  For example, for port 1:
> 
> new_parent = clk_set_parent(utmi_p1_clk, init_60m_clk);
> /* test new_parent for error */
> /* delay 1ms */
> new_parent = clk_set_parent(utmi_p1_clk, xclk60mhsp1_ck);

ok, so if I understood correctly, xclk60mhsp1_ck is the external clock
for port 1 and init_60m_clk is the internal optional 60MHz clock, right?
So the final workaround would be something like:

clk = uhh->utmi_p1_fck;

/* ensure optional clock is disabled */
clk_disable(clk);

ret = clk_set_parent(clk, parent);
if (ret) {
        dev_err(uhh->dev, "can't change %s's parent to %s\n",
                clk->name, parent->name);
        return;
}

ret = clk_enable(clk);
if (ret) {
        dev_err(uhh->dev, "failed to enable %s\n", clk->name);
        return;
}

/* wait 1ms */
msleep(1);

parent = uhh->xclk60mhsp1_ck;
clk_disable(clk);

ret = clk_set_parent(clk, parent);
if (ret) {
        dev_err(uhh->dev, "can't change %s's parent to %s\n",
                clk->name, parent->name);
        return;
}

ret = clk_enable(clk);
if (ret) {
dev_err(uhh->dev, "failed to enable %s\n", clk->name);
}

and similarly for port 2, but :%s/p1/p2/g

right ?

-- 
balbi

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