From: Santosh Shilimkar <[email protected]>

Local timer clock is sourced from the CPU clock and hence changes
along with CPU clock. These per CPU local timers are used as
clock-events, so they need to be reconfigured on CPU frequency
change as part of CPUfreq governor.

Newly introduced clockevents_reconfigure() needs to know the
twd clock-rate. Provide a clock-node to make clk_get_rate() work
for TWD.

Signed-off-by: Santosh Shilimkar <[email protected]>
Cc: Paul Walmsley <[email protected]>
Cc: Kevin Hilman <[email protected]>
[[email protected]: renamed clock node to 'mpu_periphclk' to indicate that this
 is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved
 clock and clkdev entries to match the autogenerated script output]
Signed-off-by: Paul Walmsley <[email protected]>

---
This version 3 has been updated by Santosh to use "smp_twd" as the dev_id 
and a NULL con_id, to match Linus Walleij's code.

 arch/arm/mach-omap2/clock44xx_data.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c 
b/arch/arm/mach-omap2/clock44xx_data.c
index 0798a80..730097e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1206,6 +1206,14 @@ static struct clk l4_wkup_clk_mux_ck = {
        .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk mpu_periphclk = {
+       .name           = "mpu_periphclk",
+       .parent         = &dpll_mpu_ck,
+       .ops            = &clkops_null,
+       .fixed_div      = 2,
+       .recalc         = &omap_fixed_divisor_recalc,
+};
+
 static struct clk ocp_abe_iclk = {
        .name           = "ocp_abe_iclk",
        .parent         = &aess_fclk,
@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     
CK_443X),
        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, 
CK_443X),
        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    
CK_443X),
+       CLK("smp_twd",  NULL,                           &mpu_periphclk, 
CK_443X),
        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  
CK_443X),
        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      
CK_443X),
        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       
CK_443X),
-- 
1.7.4.1

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