Hi On Tue, 24 Jan 2012, Palande, Ameya wrote:
> Any update on this? Looks good to me, but have the scripts been updated? Also could you please cc [email protected]? - Paul > > On Fri, Jan 20, 2012 at 11:53 AM, Palande, Ameya <[email protected]> wrote: > > Any update on this? > > > > On Thu, Jan 19, 2012 at 11:22 AM, Ameya Palande <[email protected]> > > wrote: > >> From: Rajendra Nayak <[email protected]> > >> > >> All DPLLs except USB are in ALWON powerdomain. Make sure the > >> clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting > >> a DPLL relock. So, mark the database accordingly. > >> > >> Without this fix, it was seen that DPLL relock fails while testing > >> relock in a loop of USB DPLL. > >> > >> CC: Nishanth Menon <[email protected]> > >> Tested-by: Ameya Palande <[email protected]> > >> Signed-off-by: Rajendra Nayak <[email protected]> > >> --- > >> arch/arm/mach-omap2/clock44xx_data.c | 1 + > >> 1 files changed, 1 insertions(+), 0 deletions(-) > >> > >> diff --git a/arch/arm/mach-omap2/clock44xx_data.c > >> b/arch/arm/mach-omap2/clock44xx_data.c > >> index 08e86d7..9519374 100644 > >> --- a/arch/arm/mach-omap2/clock44xx_data.c > >> +++ b/arch/arm/mach-omap2/clock44xx_data.c > >> @@ -974,6 +974,7 @@ static struct clk dpll_usb_ck = { > >> .recalc = &omap3_dpll_recalc, > >> .round_rate = &omap2_dpll_round_rate, > >> .set_rate = &omap3_noncore_dpll_set_rate, > >> + .clkdm_name = "l3_init_clkdm", > >> }; > >> > >> static struct clk dpll_usb_clkdcoldo_ck = { > >> -- > >> 1.7.4.1 > >> > - Paul
