From: Mythri P K <mythr...@ti.com>
While calculating regm and regmf value add M2 divider in the equation.
Signed-off-by: Mythri P K <mythr...@ti.com>
---
drivers/video/omap2/dss/hdmi.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 92a6679..9185630 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -256,24 +256,24 @@ static void hdmi_compute_pll(struct omap_dss_device
*dssdev, int phy,
refclk = clkin / pi->regn;
- /*
- * multiplier is pixel_clk/ref_clk
- * Multiplying by 100 to avoid fractional part removal
- */
- pi->regm = (phy * 100 / (refclk)) / 100;
-
if (dssdev->clocks.hdmi.regm2 == 0)
pi->regm2 = HDMI_DEFAULT_REGM2;
else
pi->regm2 = dssdev->clocks.hdmi.regm2;
/*
+ * multiplier is pixel_clk/ref_clk
+ * Multiplying by 100 to avoid fractional part removal
+ */
+ pi->regm = (phy * 100 * pi->regm2 / (refclk)) / 100;
+
+ /*
* fractional multiplier is remainder of the difference between
* multiplier and actual phy(required pixel clock thus should be
* multiplied by 2^18(262144) divided by the reference clock
*/
- mf = (phy - pi->regm * refclk) * 262144;
- pi->regmf = mf / (refclk);
+ mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
+ pi->regmf = pi->regm2 * mf / refclk;
/*
* Dcofreq should be set to 1 if required pixel clock
--
1.7.5.4
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