Hi, On Thu, 2012-02-09 at 12:14 +0530, Archit Taneja wrote: > For DSS clock domain to transition from idle to active state, it's necessary > to enable the optional clock DSS_FCLK before we enable the module using the > MODULEMODE bits in the DSS clock domain's CM_DSS_DSS_CLKCTRL register. > > This sequence was not followed correctly for the 'dss_hdmi' hwmod and it led > to DSS clock domain not getting out of idle when pm_runtime_get_sync() was > called for hdmi's platform device. > > Since the clock domain failed to change it's state to active, the hwmod code > disables any clocks it had enabled before for this hwmod. This led to the > clock > 'dss_48mhz_clk' getting disabled. > > When hdmi's runtime_resume() op is called, the call to dss_runtime_get() > correctly enables the DSS clock domain this time. But the clock > 'dss_48mhz_clk' > disabled before is needed for HDMI's PHY to function. Hence, the driver fails
There's something wrong with the "But the clock..." sentence above. The patch looks good, but I think it'd be better to add brief HACK comments in the code also. Otherwise it's too easy to forget about this. Tomi
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