On Tue, Mar 27, 2012 at 4:33 PM, Tomi Valkeinen <[email protected]> wrote:
> On Wed, 2012-03-21 at 15:22 +0530, Chandrabhanu Mahapatra wrote:
>> DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
>> calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
>> DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
>> divisor LCD.
>>
>> Signed-off-by: Chandrabhanu Mahapatra <[email protected]>
>> ---
>>  drivers/video/omap2/dss/dispc.c |   13 +++++++------
>>  1 files changed, 7 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/video/omap2/dss/dispc.c 
>> b/drivers/video/omap2/dss/dispc.c
>> index d8a1672..1fdac73 100644
>> --- a/drivers/video/omap2/dss/dispc.c
>> +++ b/drivers/video/omap2/dss/dispc.c
>> @@ -1761,6 +1761,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane 
>> plane,
>>                               dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
>>       const int max_decim_limit = 16;
>>       unsigned long fclk = 0;
>> +     unsigned long dispc_core_clk = dispc_mgr_lclk_rate(channel);
>
> Hmm, I don't think this is correct. dispc_mgr_lclk_rate() returns the
> logic clock for the LCD output path. It's not DISPC core clock.
>
>  Tomi
>

As per the OMAP4 TRM DISPC_CORE_CLK is DISPC_FCLK / LCD factor and
dispc_mgr_lclk_rate() exactly does the same. Should we rename the
function or have a separate fucntion for dispc_core_clk to avoid
confusion?

-- 
Chandrabhanu Mahapatra
Texas Instruments India Pvt. Ltd.
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