Hi,

> +/*
> + * clkdiv32 is generated from fixed division of 732.4219
> + */
> +static struct clk clkdiv32k_ick = {
> +     .name           = "clkdiv32k_ick",
> +     .clkdm_name     = "clk_24mhz_clkdm",
> +     .rate           = 32768,
> +     .parent         = &clk_24mhz,
> +     .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
> +     .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
> +     .ops            = &clkops_omap2_dflt,
> +};

While working on this file, this clock seemed quite perplexing.  Perhaps 
you might be able to answer some questions about it.

- The fractional fixed division seems a little bogus.  Is this actually an 
M,N counter?  A few moments with PARI revealed a likely M,N of 64,46875.  
Could you please confirm that this is the case for this clock?

- This clock structure makes this clock appear to be a fixed-frequency 
clock.  But according to SPRUH73D Figure 8-10 "Peripheral PLL Structure", 
the divider feeding this clock can be switched between an M,N of 64,46875 
and 32,46875 depending on the value of CONTROL_CLK32K_DIVRATIO_CTRL.  So 
shouldn't we implement that?

- This clock is feeding downstream clocks, but it's using the MODULEMODE 
control interface, as if it were a standalone IP block.  Do you know why 
it's using the MODULEMODE control method rather than some optional clock 
control bits, like OMAP4 does?


- Paul
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