Hello Tomi,
On Mon, 14 May 2012, Tomi Valkeinen wrote:
> I've been doing testing to understand the problem, but so far I don't
> have any idea why things go wrong. I haven't found out any logic in
> which configuration works and which doesn't. Looks to me that for some
> reason the PM prevents DSS from getting data fast enough with certain
> fifo thresholds.
>
> I have two ways to avoid the problem, but I've been reluctant to make
> patches for those because I feel it's just hiding the problem. One way
> is to change DISPC SIDLEMODE or MIDLEMODE to disallow idle/standby. The
> other is to use certain fifo threshold values, which just seem to work
> for unknown reasons.
>
> Considering that we already have a SIDLEMODE hack in DSS for omap3 when
> using DSI, I wonder if the omap3 PM + DSS combination is just plain
> broken, and we should disallow idle. I'm not quite sure what are the
> implications of that.
>
> I'd appreciate comments from the PM people =).
This may be caused by one of the DPLLs going into autoidle. This can
involve a significant wakeup latency. I'd suggest looking at DPLL3, which
provides the DSS interface clock, and DPLL4, which can provide the DSS
functional clock.
Could you try:
1. applying something like the patch at the bottom of this message and
seeing if it makes any difference?
2. if #1 does not work, changing the "dpll3" in the patch to "dpll4" ?
3. if #2 does not work, disabling autoidle on both dpll3 and dpll4?
I regret that I haven't been able to focus more on DSS issues -
- Paul
Date: Wed, 14 Mar 2012 17:49:43 -0600 (MDT)
From: Paul Walmsley <p...@pwsan.com>
Subject: Patch that should disable DPLL3 autoidle
Test patch to disable DPLL3 autoidle.
---
arch/arm/plat-omap/clock.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b5..4b02b35 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -351,6 +351,13 @@ int omap_clk_enable_autoidle_all(void)
if (c->ops->allow_idle)
c->ops->allow_idle(c);
+ c = clk_get(NULL, "dpll3_ck");
+ if (c && c->ops->deny_idle)
+ c->ops->deny_idle(c);
+ else
+ WARN(1, "Cannot disable autoidle on DPLL3\n");
+ clk_put(c);
+
spin_unlock_irqrestore(&clockfw_lock, flags);
return 0;
--
1.7.9.1
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