On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote:
> On 12/11/12 08:38, Will Deacon wrote:
> > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > index cd95664..f58248f 100644
> > --- a/arch/arm/mm/cache-v7.S
> > +++ b/arch/arm/mm/cache-v7.S
> > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all)
> > ENTRY(v7_flush_dcache_louis)
> > dmb @ ensure ordering with
> > previous memory accesses
> > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> > mov r3, r3, lsr #20 @ r3 = LoUIS * 2
>
> You need to fix this mov as well, right?
Ha, nice catch. So the original patch ended up with a ridiculously high
level number and would've flushed L2, hence we will need to retest with the
fix below...
Will
--->8
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index cd95664..7539ec2 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
ENTRY(v7_flush_dcache_louis)
dmb @ ensure ordering with previous
memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
- ands r3, r0, #0xe00000 @ extract LoUIS from clidr
- mov r3, r3, lsr #20 @ r3 = LoUIS * 2
+ ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
+ ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
+ ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
+ ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
moveq pc, lr @ return if level == 0
mov r10, #0 @ r10 (starting level) = 0
b flush_levels @ start flushing cache levels
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