Hi all,
I'm reading OMAP5's smp boot codes and have got a question.
>From my understanding, the omap4_omap_prepare_cpus() would set the startup
address of secondary core, while omap4_boot_secondary() would set AuxCoreBoot0
to 0x20 which may make the omap5_secondary_startup() jump out of "wait loop"
to secondary_startup.
And the comment in omap4_smp_prepare_cpus says:
Write the address of secondary startup routine into the
AuxCoreBoot1 where ROM code will jump and start executing
on secondary core once out of *WFE*
My question is: How will ROM code be out of WFE? Is it waked up by dsb_sev()
in omap4_boot_secondary()?
If so, how should I understand the comment in omap4_boot_secondary():
Update the AuxCoreBoot0 with boot state for secondary core.
omap4(5)_secondary_startup() routine will hold the secondary core till
the AuxCoreBoot1 register is update with cpu state.
^^^^^^^^^^^^ Since the entry to omap5_secondary_startup() is set up
by AuxCoreBoot1, it seems a chicken and egg problem.
And I didn't see any codes deal with AuxCoreBoot1 in
either omap4_secondary_startup() or
omap5_secondary_startup().
Thanks.
Chen Baozi
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