Hi, I have started working on implementing cacheinfo support for OpenRISC, and I have got a few queries.
Q1. Does OpenRISC support multilevel cache hierarchy? I couldn't find anything in the architecture manual [1] mentioning the possibility of a multilevel cache hierarchy. I wasn't able to find anything in the verilog implementation either [2]. Q2. In /sys/devices/system/cpu/cpuX/cache, each indexY directory corresponds to a CPU cache. According to the OpenRISC 1000 Architecture specification [1], it is possible to have a unified cache. In such a case, registers controlling the instruction and data cache represent the same thing (section 9.1 of the manual). Consequently, should there be only one index (i.e. index0), or should there be 2 index directories (index0 and index1) with identical content? If aunified cache is used, will the DCP and ICP bits both be set in the UPR register? Q3. Cache-related arithmetic performed in arch/openrisc/kernel/setup.c:setup_cpuinfo() [3] cannot be avoided. But we can expose this info in sysfs instead of cpuinfo as specified in this mail [4]. So, I was thinking of moving these calculations to arch/openrisc/kernel/cacheinfo.c in init_cache_level(). What are your thoughts on this? Another thing I noticed in the current implementation is that these calculations are performed for icache and dcache before using the UPR register to check if they even exist. Should these calculations instead be performed after determining that they exist? Thanks, Sahil [1] https://openrisc.io/or1k.html [2] https://github.com/openrisc/mor1kx [3] https://github.com/openrisc/linux/blob/for-next/arch/openrisc/kernel/setup.c#L155 [4] https://lkml.org/lkml/2017/3/14/620
