Hello, Replying Again, as last mail had html and didn't make it to the list.
On Fri, Mar 07, 2025 at 12:08:14PM +0000, Idzwan Nizam Jamal Abdul Nasir wrote: > > Does it mean I need to send a proposal like a student who's joining GSOC too? Sorry no, there is no need if you are not doing gsoc. If you can make progress before gsoc starts I can stear students away from this project. But please just post your interest and progress on the mailing list. -Stafford > On Thursday, March 6, 2025 at 11:39:13 PM GMT+8, Stafford Horne > <[email protected]> wrote: > > On Mon, Mar 03, 2025 at 02:11:06AM +0000, Idzwan Nizam Jamal Abdul Nasir > wrote: > > Hi, > > > > I am interested in OpenRISC Benchmarking and Performance improvements task > > listed as one of the project ideas in Google Summer of Code. I am unable to > > participate in GSOC but I would like to contribute to the task gradually as > > I > > acquire skills in digital logic and computer architecture. > > > > Is the task still open? I would be glad if you could point me to the right > > direction such as documentation I should read or tools I have to be familiar > > with. Any guidance is welcome and greatly appreciated. Thank you. > > The task is still open. There are other students interested so I will have to > end up having to choose the student with the best proposal and skill. > > Please try to get started by reading up on what was done last year in this > space and see if you can follow some of the steps to get the development > environment setup. > > Our previous GSoC participant, Leo, did a lot of ground work but never > submitted > any formal GSoC progress report or documentation. > > What he did produce were: > > Here's the embench-iot with fusesoc compatability changes applied: > https://github.com/hhe07/embench-or-patched > > And here's some tools I made for working with instruction printouts on > posedge: > https://codeberg.org/hhe07/or-analysis-utils > > He started this blog with details of how to get OpenRISC simulations working > with Litex or FuseSoC. > > https://hhe07.codeberg.page/openrisc-work/ > > What we want to do is: > > *Getting started* > 1 Get openrisc mor1kx and maroccino working in embench-iot > a. With SoC, either fusesoc or litex (fusesoc should be easier) > b. With backend, either icarus or verilator (verilator seems to run > faster) > c. Serial output needs to work to be able to capture timing information or > when tests start and stop. In verilator this is a bit tricky but should > work with the proper flags. > *Recording Results* > 2 We next want to record reults in a format similar to > embench-iot-results[0] > a. Collect results for default maroccino, mor1kx > b. Collect results with permutations of cpu and compiler config > i. Caches of difference sizes, enabled/disabled, different branch > prediction algorithms, different ALU implementations, etc. > ii. Certain instructions enabled/disabled by the compiler, -mror, > -msfimm > etc see `or1k-elf-gcc --target-help` (Note: the project aims to > benchmark both CPU pipeline, compiler and instruction set > efficiency) > *Improving results* > 3 We next can look at where the cpus are lacking performance and how to > improve things in the pipeline, LSU, caches etc. > 4 We can then go back to 2 (Record results again) and compare. > > The 2024 GSoC project was only able to get done with steps in 1 and just > started > with 2.a. I think there is a lot of work left to be done, getting done with 2 > for a GSoC project would be a great accomplishment. > > [0] https://github.com/embench/embench-iot-results > >
