Update for this issue. - rc0 and instruction events show the similar result. - still, the count of L3 cache miss event is 1/10 of what i expected. (LLC-load-misses)
2012-11-26 오후 8:24, Chulmin Kim 쓴 글: > Hi all. > > I'm on the way of monitoring AMD machine. > > I wonder Perf is supporting AMD PMU Events perfectly or not. > > It seems not working correctly despite the same command works in intel > machines perfectly. > > command : (perf stat -e rc0 -e instructions ./blah) > result : the value for "rc0" almost equals to that of "instruction" in > Intel machine, while it does not in AMD machine > > > Other events such as cache events seem weird also. > > Is there any material mentioning this issue? > > > > Thanks! > > -- > To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
