Henrik Schmiediche wrote: > My original question (turning of ECC for memory testing) was hopefully going > to narrow down the issue. >
It's probably possible to disable ECC after boot time using setpci (I've used it to read and write the ECC status registers on Intel chipsets in the past), but I don't know the details of the i5000 ECC implementation (I don't even know if the ECC functionality is still controlled via PCI Configuration space) - you'll have to check the datasheet (or the i5000_edac driver source). ISTR, memtest86 and memtest86+ both had some functionality for reading/writing ECC status bits on some chipsets as well, so you could hack on these too (but the code was a bit messed up last time I looked - I think ECC "no", and ECC "NO" had different meanings!)... Tim. -- South East Open Source Solutions Limited Registered in England and Wales with company number 06134732. Registered Office: 2 Powell Gardens, Redhill, Surrey, RH1 1TQ VAT number: 900 6633 53 http://seoss.co.uk/ +44-(0)1273-808309 _______________________________________________ Linux-PowerEdge mailing list [email protected] https://lists.us.dell.com/mailman/listinfo/linux-poweredge Please read the FAQ at http://lists.us.dell.com/faq
