On Thu, Oct 11, 2012 at 10:44 PM, Roland Dreier <[email protected]> wrote:

> No one has really ever tried to deal with the issue of userspace RDMA on
> a cache-incoherent architecture.  Basically if you try the current stack, the
> in-kernel users (IPoIB etc) should be OK but libibverbs etc. will be 
> completely broken.

I think the question might refer even to cache-coherent systems, e.g
in the kernel IB core and ULPs all buffers are dma mapped to/from the
device before/after they are touched by the CPU and vise versa, wheres
in user space, after the buffers are registered once, they are
repeatedly touched by the CPUs and provided to the HW for DMA, e.g all
user space buffers are treated like kernel DMA coherent ones.

Or.
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