From: Manikanta Mylavarapu <quic_mmani...@quicinc.com>
IPQ5332 security software running under trustzone requires metadata size.
With new command support added in TrustZone that includes a size parameter,
pass metadata size as well.
Signed-off-by: Manikanta Mylavarapu <quic_mmani...@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <gokul.srira...@oss.qualcomm.com>
---
drivers/firmware/qcom/qcom_scm.c | 17 +++++++++++++----
drivers/firmware/qcom/qcom_scm.h | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index fc4d67e4c4a6..456e4de538b2 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -583,9 +583,6 @@ int qcom_scm_pas_init_image(u32 peripheral, const void
*metadata, size_t size,
int ret;
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
- .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
- .args[0] = peripheral,
.owner = ARM_SMCCC_OWNER_SIP,
};
struct qcom_scm_res res;
@@ -617,7 +614,19 @@ int qcom_scm_pas_init_image(u32 peripheral, const void
*metadata, size_t size,
if (ret)
goto disable_clk;
- desc.args[1] = mdata_phys;
+ if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
+ QCOM_SCM_PIL_PAS_INIT_IMAGE_V2)) {
+ desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE_V2;
+ desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW,
QCOM_SCM_VAL);
+ desc.args[0] = peripheral;
+ desc.args[1] = mdata_phys;
+ desc.args[2] = size;
+ } else {
+ desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE;
+ desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
+ desc.args[0] = peripheral;
+ desc.args[1] = mdata_phys;
+ }
ret = qcom_scm_call(__scm->dev, &desc, &res);
qcom_scm_bw_disable();
diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h
index 097369d38b84..0f40e5828a67 100644
--- a/drivers/firmware/qcom/qcom_scm.h
+++ b/drivers/firmware/qcom/qcom_scm.h
@@ -96,6 +96,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void);
#define QCOM_SCM_SVC_PIL 0x02
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
+#define QCOM_SCM_PIL_PAS_INIT_IMAGE_V2 0x1a
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
--
2.34.1
