Hi Laurent > > > The parent clock isn't documented in the datasheet, use S2D1 as a best > > > guess for now. > > > > Would you be able to find out what the parent clock is for the FCP and LVDS > > (patch 2/9) clocks ?
It seems FCP clock is based on each SoC In H3 ES1 case, it is using - s2d2 (for 200MHz) - s2d1 (for 400MHz)
