Hello all,
Today I realized that the clock control using clk-mstp has never actually
worked for RZ/A1 (r7s72100).
The reason is that the MSTP registers are 8-bit instead of the normal 32-bit,
and if you do a 32-bit write to them, nothing happens.
If you look in drivers/clk/renesas/clk-mstp.c, you'll see that clk_readl and
clk_writel are used.
The reason why I have gotten this far is because u-boot has been enabling
everything early in boot, so all the clocks were already on.
Of course if I disable everything again before I booting the kernel....nothing
works.
If I change the accesses in clk-mspt.c to 8-bit, clocks get enabled/disabled as
they should.
#define clk_readl readb
#define clk_writel writeb
So, any suggestions on the best way to fix this???
Ideally I would like something that can easily be integrated back into 4.9.x
Maybe add a new DT property named "reg_width":
mstp3_clks: mstp3_clks@fcfe0420 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xfcfe0420 4>;
reg_width = 8;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_MTU2>;
clock-output-names = "mtu2";
};
and then in cpg_mstp_clocks_init(), do:
if (of_find_property(np, "reg_width", &i))
group->reg_width = i;
else
group->reg_width = 32; /* default */
In cpg_mstp_clock_endisable(), do:
if (group->reg_width == 8)
writeb(value, group->smstpcr);
else
clk_writel(value, group->smstpcr);
Thoughts?
Chris
