On Monday, January 09, 2017, Laurent Pinchart wrote: > Pin control on the Renesas RZ chips is performed per pin instead of per > function (but unfortunately with the various bits of configuration split > across a bunch of registers, otherwise we could have used pinctrl-single).
I will say this...'spoilier alert'...you're not going to see this particular PFC HW much anymore in the RZA series. It will still be a 'per pin control' like the existing RZ/A1, but the bits will not be spread out over a bunch of registers. So something like pinctrl-single should work. No idea about the future of RZG series. > This gives us an opportunity to move away from the sh-pfc awful (but more > or less needed for the R-Car family) architecture and implement something > much, much cleaner without all those obscure data tables and macros, with > per-pin configuration. Shouldn't we rejoice and embrace that opportunity ? Honestly, that driver structure confuses the heck out of me. I guess you have to understand the restrictions of the R-Car PFC HW to really appreciate it. Of course I like the idea of a simple PFC for Renesas SoCs, of course the existing RZ/A1 would be (hopefully) the worst case scenario. I assume to make a one-size-fits-all per-pin driver, instead of filling out structures and enums, you'd have to have callback functions that basically you pass "set pin X to function #3"...which basically brings you back to what the core of the pinctrl system does now any (if I understand it correctly). Chris
