On Tue, Jan 17, 2017 at 8:59 PM, Chris Brandt <chris.bra...@renesas.com> wrote:
> The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
> need to be enabled/disabled for proper operation. This fixes the fact that
> the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
> that all 4 clock sources need to be defined an used.
>
> Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Note that this depends on the acceptance of the DT binding doc update.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
