When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.
Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to
dtsi")
Signed-off-by: Chris Brandt <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v3:
* changed clk_readl to cpg_mstp_read to take into account 8-bit registers
* added Reviewed by Geert Uytterhoeven
v2:
* added Fixes because technically this is a bug fix
---
drivers/clk/renesas/clk-mstp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 3ce819c..4067216 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool
enable)
value |= bitmask;
cpg_mstp_write(group, value, group->smstpcr);
+ if (!group->mstpsr) {
+ /* dummy read to ensure write has completed */
+ cpg_mstp_read(group, group->smstpcr);
+ barrier_data(group->smstpcr);
+ }
+
spin_unlock_irqrestore(&group->lock, flags);
if (!enable || !group->mstpsr)
--
2.10.1
