From: Geert Uytterhoeven <geert+rene...@glider.be>

The Cortex-A15/A7 cache controllers are integrated controllers, and thus
the device nodes representing them should not have unit-addresses or reg
properties.

Fixes: b0da45c60d2f7b08 ("ARM: dts: r8a73a4: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
 arch/arm/boot/dts/r8a73a4.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 00eb9a7114dc..6fb7eaba9126 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -32,18 +32,16 @@
                        next-level-cache = <&L2_CA15>;
                };
 
-               L2_CA15: cache-controller@0 {
+               L2_CA15: cache-controller-0 {
                        compatible = "cache";
-                       reg = <0>;
                        clocks = <&cpg_clocks R8A73A4_CLK_Z>;
                        power-domains = <&pd_a3sm>;
                        cache-unified;
                        cache-level = <2>;
                };
 
-               L2_CA7: cache-controller@100 {
+               L2_CA7: cache-controller-1 {
                        compatible = "cache";
-                       reg = <0x100>;
                        clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
                        power-domains = <&pd_a3km>;
                        cache-unified;
-- 
2.7.0.rc3.207.g0ac5344

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