> -----Original Message-----
> From: Wolfram Sang [mailto:[email protected]]
> Sent: 03 August 2017 08:43
> To: Biju Das <[email protected]>
> Cc: Wolfram Sang <[email protected]>; linux-renesas-
> [email protected]; Simon Horman <[email protected]>; Yoshihiro
> Shimoda <[email protected]>; linux-mmc-
> [email protected]
> Subject: Re: [PATCH 4/4] mmc: sdhi: use maximum width for the sdbuf register
>
> > [ 1.162808] sh_mobile_sdhi ee140000.sd: Got CD GPIO
> > [ 1.167721] sh_mobile_sdhi ee140000.sd: Got WP GPIO
> > [ 1.225803] bus_width: 0
>
> This should be '1'.
>
> Which tree is this based on? I can't find SDHI nodes for r8a7743 in its dtsi
> file in
> linux-next? I'd think the node is not correct.
It is not upstreamed yet. I am going to upstream this patches with in a week or
two.
Currently this patch is under internal review.
It is identical to R-Car M2.I believe this issue should reproducible with R-Car
M2-W board(r8a7791).
I first rebased my SDHI patches with renesas-dev branch and it worked fine.
Then I rebased the same patches on linux-next + relevant patches from
renesas-dev , it is started showing the issue.
Then I found that this patch is causing the issue.
Please find the DT related entries here.
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index 4fd8b7a..0d507ec 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -15,6 +15,8 @@ Required properties:
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
+"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
@@ -34,8 +36,8 @@ Required properties:
"core" and "cd". If the controller only has 1 clock, naming is not
required.
Below is the number clocks for each supported SoC:
- 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
- R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
+ 1: SH73A0, R8A73A4, R8A7740, R8A7743, R8A7745, R8A7778, R8A7779,
+ R8A7790, R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
2: R7S72100
Optional properties:
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b3a1efa..b5ac0ff 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -19,6 +19,29 @@
serial0 = &scif0;
ethernet0 = &avb;
};
+
+vcc_sdhi1: regulator-vcc-sdhi1 {
+compatible = "regulator-fixed";
+
+regulator-name = "SDHI1 Vcc";
+regulator-min-microvolt = <3300000>;
+regulator-max-microvolt = <3300000>;
+
+gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+};
+
+vccq_sdhi1: regulator-vccq-sdhi1 {
+compatible = "regulator-gpio";
+
+regulator-name = "SDHI1 VccQ";
+regulator-min-microvolt = <1800000>;
+regulator-max-microvolt = <3300000>;
+
+gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+gpios-states = <1>;
+states = <3300000 1
+ 1800000 0>;
+};
};
&pfc {
@@ -36,6 +59,18 @@
groups = "i2c2";
function = "i2c2";
};
+
+sdhi1_pins: sd1 {
+groups = "sdhi1_data4", "sdhi1_ctrl";
+function = "sdhi1";
+power-source = <3300>;
+};
+
+sdhi1_pins_uhs: sd1_uhs {
+groups = "sdhi1_data4", "sdhi1_ctrl";
+function = "sdhi1";
+power-source = <1800>;
+};
};
&scif0 {
@@ -72,3 +107,16 @@
reg = <0x68>;
};
};
+
+&sdhi1 {
+pinctrl-0 = <&sdhi1_pins>;
+pinctrl-1 = <&sdhi1_pins_uhs>;
+pinctrl-names = "default", "state_uhs";
+
+vmmc-supply = <&vcc_sdhi1>;
+vqmmc-supply = <&vccq_sdhi1>;
+cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+sd-uhs-sdr50;
+status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index ff79938..4119737 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -9,6 +9,7 @@
*/
#include "r8a7743.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "iwave,g20m", "renesas,r8a7743";
@@ -42,6 +43,12 @@
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
+
+sdhi0_pins: sd0 {
+groups = "sdhi0_data4", "sdhi0_ctrl";
+function = "sdhi0";
+power-source = <3300>;
+};
};
&mmcif0 {
@@ -53,3 +60,13 @@
non-removable;
status = "okay";
};
+
+&sdhi0 {
+pinctrl-0 = <&sdhi0_pins>;
+pinctrl-names = "default";
+
+vmmc-supply = <®_3p3v>;
+vqmmc-supply = <®_3p3v>;
+cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 5c2b140..8945cc7 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -834,6 +834,48 @@
max-frequency = <97500000>;
status = "disabled";
};
+
+sdhi0: sd@ee100000 {
+compatible = "renesas,sdhi-r8a7743";
+reg = <0 0xee100000 0 0x328>;
+interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+clocks = <&cpg CPG_MOD 314>;
+dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+dma-names = "tx", "rx", "tx", "rx";
+max-frequency = <195000000>;
+power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+resets = <&cpg 314>;
+status = "disabled";
+};
+
+sdhi1: sd@ee140000 {
+compatible = "renesas,sdhi-r8a7743";
+reg = <0 0xee140000 0 0x100>;
+interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+clocks = <&cpg CPG_MOD 312>;
+dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+dma-names = "tx", "rx", "tx", "rx";
+max-frequency = <97500000>;
+power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+resets = <&cpg 312>;
+status = "disabled";
+};
+
+sdhi2: sd@ee160000 {
+compatible = "renesas,sdhi-r8a7743";
+reg = <0 0xee160000 0 0x100>;
+interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+clocks = <&cpg CPG_MOD 311>;
+dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+dma-names = "tx", "rx", "tx", "rx";
+max-frequency = <97500000>;
+power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+resets = <&cpg 311>;
+status = "disabled";
+};
};
/* External root clock */
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 642a0dc..a90edb5 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -93,6 +93,8 @@
{ .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
{ .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
{ .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
+{ .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
+{ .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
