Enable PCIe Controller & set PCIe bus clock frequency. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> --- This patch has dependency on below patch
* ARM: dts: iwg20d-q7-common: Add can0 support to carrier board https://patchwork.kernel.org/patch/10046879/ arch/arm/boot/dts/iwg20d-q7-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 3e4bc4d..54470c6 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -96,6 +96,14 @@ pinctrl-names = "default"; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + status = "okay"; +}; + &pfc { can0_pins: can0 { groups = "can0_data_d"; -- 1.9.1
