On Fri, Feb 16, 2018 at 3:25 PM, Ulrich Hecht
<ulrich.hecht+rene...@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara...@renesas.com>
>
> This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
> NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
> definition name to SEL_NDFC.
>
> This is a correction to the incorrect implementation of MOD_SEL register
> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
> User's Manual Rev.0.53E.
>
> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
and queueing in sh-pfc-for-v4.17.
I guess this applies to M3-N, too?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
