It was though all ES revisions of H3 and M3-W SoCs required the
TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is
not true, only early ES revisions of the SoC do.
Since quirk matching based on ES revisions is now used to handle the
flag it's possible to align all Gen3 compatibility properties. This will
allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400
mode.
Signed-off-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 20 ++-----------------
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 17 ++--------------
2 files changed, 4 insertions(+), 33 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 35cc0de6be67a515..d032bd63444d1029 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -82,22 +82,6 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
},
};
-static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
- TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
- TMIO_MMC_HAVE_4TAP_HS400,
- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
- MMC_CAP_CMD23,
- .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
- .bus_shift = 2,
- .scc_offset = 0x1000,
- .taps = rcar_gen3_scc_taps,
- .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
- /* DMAC can handle 0xffffffff blk count but only 1 segment */
- .max_blk_count = 0xffffffff,
- .max_segs = 1,
-};
-
static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
@@ -114,8 +98,8 @@ static const struct renesas_sdhi_of_data
of_rcar_gen3_compatible = {
};
static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
- { .compatible = "renesas,sdhi-r8a7795", .data =
&of_rcar_r8a7795_compatible, },
- { .compatible = "renesas,sdhi-r8a7796", .data =
&of_rcar_r8a7795_compatible, },
+ { .compatible = "renesas,sdhi-r8a7795", .data =
&of_rcar_gen3_compatible, },
+ { .compatible = "renesas,sdhi-r8a7796", .data =
&of_rcar_gen3_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data =
&of_rcar_gen3_compatible, },
{},
};
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 890f192dedbdcc9c..4bb46c489d71f848 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -78,19 +78,6 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
},
};
-static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
- TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
- TMIO_MMC_HAVE_4TAP_HS400,
- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
- MMC_CAP_CMD23,
- .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
- .bus_shift = 2,
- .scc_offset = 0x1000,
- .taps = rcar_gen3_scc_taps,
- .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
-};
-
static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
@@ -117,8 +104,8 @@ static const struct of_device_id
renesas_sdhi_sys_dmac_of_match[] = {
{ .compatible = "renesas,sdhi-r8a7792", .data =
&of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7793", .data =
&of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7794", .data =
&of_rcar_gen2_compatible, },
- { .compatible = "renesas,sdhi-r8a7795", .data =
&of_rcar_r8a7795_compatible, },
- { .compatible = "renesas,sdhi-r8a7796", .data =
&of_rcar_r8a7795_compatible, },
+ { .compatible = "renesas,sdhi-r8a7795", .data =
&of_rcar_gen3_compatible, },
+ { .compatible = "renesas,sdhi-r8a7796", .data =
&of_rcar_gen3_compatible, },
{ .compatible = "renesas,rcar-gen1-sdhi", .data =
&of_rcar_gen1_compatible, },
{ .compatible = "renesas,rcar-gen2-sdhi", .data =
&of_rcar_gen2_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data =
&of_rcar_gen3_compatible, },
--
2.18.0
