Hi Geert,
On Wednesday, August 08, 2018, Geert Uytterhoeven wrote:
> Suggestions for actions:
> 1. Revert commit 7acece71a517cad8 ("serial: sh-sci: Remove
> SCIx_RZ_SCIFA_REGTYPE"), as this is a dependency for step 2,
> 2. Revert commit 2d4dd0da45401c7a ("serial: sh-sci: Allow for compressed
> SCIF address"), to unbreak earlycon on RZ/A1, RZ/G, and R-Car SCIF
> ports,
Oh well. The idea of a shared SCIF regtype was a good idea...just too
much baggage to deal with.
> 4. Drop "renesas,scif" from the compatible value in the (not yet
> submitted) r7s9210.dtsi (this may have to be clarified in the DT
> bindings, although they already say "renesas,scif" is only meant for
> ports compatible with the generic version, whatever that means ;-),
As soon as I update to the new clock driver style and get that
mainlined, then I can submit the r7s9210.dtsi.
> 5. Add an OF_EARLYCON_DECLARE() for RZ/A2, setting port_cfg.regtype to
> SCIx_RZ_SCIFA_REGTYPE, to (presumably) make earlycon work on RZ/A2,
This is the one that I was happy to learn how to do it since originally
I wasn't sure how I could get earlycon to work with the oddball RZ/A2
SCIF.
Thanks,
Chris
