Add RSPI clocks for RZ/A2.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index d8ff4cb0defc..5135f13ec628 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -95,6 +95,9 @@ static const struct mssr_mod_clk r7s9210_mod_clks[]
__initconst = {
DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
+ DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
};
/* The clock dividers in the table vary based on DT and register settings */
--
2.16.1
