Hello Biju-san, Thank you for the email.
> From: Biju Das, Sent: Monday, October 15, 2018 11:55 PM > > Hello Shimoda-San and all, > > RZ/G1C USB2.0 host/function controller has the below features compared to > R-Car Gen2/Gen3 USB2.0 block > > 1) It has a shared pll reset register for hsusb0/hsusb1 and this register > reside in hsusb0 block. > 2) This implies, in order to enable USB1 host/peripheral, we need to enable > hsusb0 block as well. > 3) USB2.0 Host controller block is similar to R-Car Gen3 USB2.0 host > controller but with > few register sets. There is no PLL reset on the host side(USBCTR). I also checked the RZ/G1C datasheet and I understood them. - Each USB host needs to deassert the pll reset only if RZ/G1C. (In other words, other RZ/G1 and R-Car Gen2/3 don't need to deassert the pll reset of hsusb block for host side.) > To address 1 and 3, I have modified the phy-rcar-gen2 with rz/g1c specific > phy_ops . > Also added optional usb2.0 host reg property for initializing interrupt > enable, OVC detection timer and Suspend/resume > timer register . If so, you also have to add optional usb2.0 host clock and enable the clock on the phy-rcar-gen2 driver. > I will send the patch based on the below discussion. > > To address 2, I am seeing 2 solutions > > solution 1) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) and > On the board dts-> enable hsusb0 + usb1 host/peripheral. > > solution 2) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) followed > by hsusb0 clock and > On the board dts-> enable only usb1 host/peripheral. > This will allow us to do pll reset without enabling > hsusb0 on the board dts. I'm afraid but I don't understand these 2 solutions. Where are the USB1 clocks defined? > Do you have any preferences one way or the other? Or a third option? I'm thinking which nodes we will have on RZ/G1C dtsi: - We will have ehci[01]/ohci[01]/hsusb[01]/usbphy[01] nodes. - ehci0/ohci0/hsusb0 nodes have phys property with usbphy0. - ehci1/ohci1/hsusb1 nodes have phys property with both usbphy0 and usbphy1 to achieve the 2) you mentioned above. - usbphy[01] has reg/clocks as both own hsusb and usb host blocks. About the phy driver: - Add the 1) and 3) you mentioned above. Best regards, Yoshihiro Shimoda > Regards, > Biju
