On Thu, Nov 01, 2018 at 12:25:18AM +0100, Niklas Söderlund wrote: > From: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se> > > On H3 (ES1.0,ES2.0) and M3-W (ES1.0,ES1.1) the clock setting for HS400 > needs a quirk to function properly. The reason for the quirk is that > there are two settings which produces same divider vale for the SDn > clock. On the effected boards the one currently selected results in HS00 > not working. > > This change uses the same method as the Gen2 CPG driver and simply > ignores the first clock setting as this is the offending one when > selecting the settings. Which of the two possible settings is used have > no effect for SDR104. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+rene...@sang-engineering.com> Tested-by: Wolfram Sang <wsa+rene...@sang-engineering.com>
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