[PATCH] arm64: dts: renesas: r8a77990: ebisu: Add and enable PCIe device node

[Marek Vasut]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds PCI express channel 0 device node to the R8A77990 SoC
and enables PCIEC0 PCI express controller on the Ebisu board.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman <horms+rene...@verge.net.au>
Cc: Wolfram Sang <w...@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda...@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
To: devicet...@vger.kernel.org
---
 .../arm64/boot/dts/renesas/r8a77990-ebisu.dts |  8 +++++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi     | 34 +++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 447e9831104a..2ef9067616ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -444,6 +444,14 @@
        status = "okay";
 };
 
+&pcie_bus_clk {
+       clock-frequency = <100000000>;
+};
+
+&pciec0 {
+       status = "okay";
+};
+
 &pfc {
        avb_pins: avb {
                mux {
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index a2524fc138a2..46868dacbeef 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -85,6 +85,13 @@
                clock-frequency = <0>;
        };
 
+       /* External PCIe clock - can be overridden by the board */
+       pcie_bus_clk: pcie_bus {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
        pmu_a53 {
                compatible = "arm,cortex-a53-pmu";
                interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -1610,6 +1617,33 @@
                        };
                };
 
+               pciec0: pcie@fe000000 {
+                       compatible = "renesas,pcie-r8a77990",
+                                    "renesas,pcie-rcar-gen3";
+                       reg = <0 0xfe000000 0 0x80000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       bus-range = <0x00 0xff>;
+                       device_type = "pci";
+                       ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 
0x00100000
+                               0x02000000 0 0xfe200000 0 0xfe200000 0 
0x00200000
+                               0x02000000 0 0x30000000 0 0x30000000 0 
0x08000000
+                               0x42000000 0 0x38000000 0 0x38000000 0 
0x08000000>;
+                       /* Map all possible DDR as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 
0x40000000>;
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic GIC_SPI 116 
IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                       clock-names = "pcie", "pcie_bus";
+                       power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                       resets = <&cpg 319>;
+                       status = "disabled";
+               };
+
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;
-- 
2.18.0