Add the definitions for can0 and can1 to the r8a7744 SoC dtsi.
Signed-off-by: Biju Das <biju....@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
V1-->V2
* No Change
---
arch/arm/boot/dts/r8a7744.dtsi | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cb6dfb5..87187f2 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -884,13 +884,31 @@
};
can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7744",
+ "renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7744_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
};
can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7744",
+ "renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7744_CLK_RCAN>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
};
rcar_sound: sound@ec500000 {
--
2.7.4
