From: Takeshi Kihara <takeshi.kihara...@renesas.com>

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Aug 24, 2018, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is
selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.

Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
To be queued in sh-pfc-for-v5.1.

 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index db8e1f1e91551b93..3ce1b24a9d6e95f2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1073,7 +1073,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP11_11_8,             RIF1_SYNC),
        PINMUX_IPSR_GPSR(IP11_11_8,             TS_SCK1),
 
-       PINMUX_IPSR_GPSR(IP11_15_12,            TX0_A),
+       PINMUX_IPSR_MSEL(IP11_15_12,            TX0_A,          SEL_SCIF0_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            HTX1_A),
        PINMUX_IPSR_MSEL(IP11_15_12,            SSI_WS2_A,      SEL_SSI2_0),
        PINMUX_IPSR_GPSR(IP11_15_12,            RIF1_D0),
@@ -1183,7 +1183,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_19_16,            SIM0_D_A,       SEL_SIMCARD_0),
 
        PINMUX_IPSR_GPSR(IP13_23_20,            MLB_DAT),
-       PINMUX_IPSR_GPSR(IP13_23_20,            TX0_B),
+       PINMUX_IPSR_MSEL(IP13_23_20,            TX0_B,          SEL_SCIF0_1),
        PINMUX_IPSR_MSEL(IP13_23_20,            RIF0_SYNC_A,    SEL_DRIF0_0),
        PINMUX_IPSR_GPSR(IP13_23_20,            SIM0_CLK_A),
 
-- 
2.17.1

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