Hi Sergei,
On Tue, Nov 27, 2018 at 4:39 PM Sergei Shtylyov
<[email protected]> wrote:
> On 11/23/2018 03:55 PM, Geert Uytterhoeven wrote:
> >> Add the RPC clock for the R-Car gen3 SoCs -- this clock is controlled by
> >> the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970).
> >>
> >> Signed-off-by: Sergei Shtylyov <[email protected]>
> >
> > Thanks for your patch!
> >
> >> --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c
> >> +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c
> >> + init.parent_names = &parent_name;
> >> + init.num_parents = 1;
> >> +
> >> + clock->reg = base + CPG_RPCCKCR;
> >> + clock->hw.init = &init;
> >> +
> >> + clk = clk_register(NULL, &clock->hw);
> >> + if (IS_ERR(clk))
> >> + kfree(clock);
> >> +
> >
> > For save/restore during system suspend/resume:
> >
> > cpg_simple_notifier_register(notifiers, &clock->csn);
>
> Done.
>
> > Hmm, looks like I missed that during review of commit 381081ffc2948e1e
> > ("clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI"), too.
>
> Want me to fix this?
Yes please. Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
