Hello Simon, Geert Thank you for your feedback!
> From: Simon Horman <[email protected]> > Sent: 25 February 2019 09:27 > Subject: Re: [PATCH] clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK > > On Fri, Feb 22, 2019 at 12:01:21PM +0000, Chris Paterson wrote: > > > > > From: Fabrizio Castro <[email protected]> > > > Sent: 22 February 2019 12:00 > > > > > > Enum LAST_DT_CORE_CLK needs updating as R8A774A1_CLK_CANFD > > > was recently added and it's the core clock with the highest > > > index. > > > > > > Signed-off-by: Fabrizio Castro <[email protected]> > > Reviewed-by: Chris Paterson <[email protected]> > > I think this needs: > > Fixes: 9d034e151b40 ("clk: renesas: r8a774a1: Add missing CANFD clock") I naively thought I could only refer to commits from Torvald's, which is clearly wrong, therefore thank you for fixing. Cheers, Fab > > Reviewed-by: Simon Horman <[email protected]> > > > > > > --- > > > drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > index 5fcd6c5..8e7bb43 100644 > > > --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > > @@ -21,7 +21,7 @@ > > > > > > enum clk_ids { > > > /* Core Clock Outputs exported to DT */ > > > - LAST_DT_CORE_CLK = R8A774A1_CLK_OSC, > > > + LAST_DT_CORE_CLK = R8A774A1_CLK_CANFD, > > > > > > /* External Input Clocks */ > > > CLK_EXTAL, > > > -- > > > 2.7.4 > >
