On 03/11/2019 08:14 PM, Sergei Shtylyov wrote:


>    No hangs were seen on V3M, despite the RPCD2 clock remained disabled.
> The RPC clocks on both V3H and V3M suffer from a lack of clear 
> documentation...
>> See also section 62.4.7 (Frequency change), which does not have a
>> subsection for V3H, but it may be impacted (changing RPCD2 causes
>> an additional read of RPCCKR, satisfying the read-after-write requirement
>> documented there).
>    Hmm, haven't seen this item before; it looks like we can't use the standard
> divider component. BTW, this section in the 1.50 manual tells to use the soft
> reset on V3MOK. OK, I'll investigate this...

   Now I have: the frequency change didn't seem to  happen, and without RPCD2 
the CMNCR read still hangs, even when I added readl() call into clk_writel(). 
So I
think my patch was correct.

>>> Fixes:  94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
>>> Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
> [...]

MBR, Sergei

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