[PATCH/RFT] arm: dts: renesas: r7s9210-rza2mevb: sort nodes of rza2mevb board

[Yoshihiro Kaneko]

This patch sorts the nodes of arch/arm/boot/dts/r7s9210-rza2mevb.dts.

* Sort subnodes of root ("/") node alphabetically
* Sort following top-level nodes alphabetically
* Sort subnodes of pinctrl alphabetically

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm/boot/dts/r7s9210-rza2mevb.dts | 92 +++++++++++++++++-----------------
 1 file changed, 46 insertions(+), 46 deletions(-)

diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts 
b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index fa44e35..71808ce 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -26,11 +26,6 @@
                stdout-path = "serial0:115200n8";
        };
 
-       memory@40000000 {
-               device_type = "memory";
-               reg = <0x40000000 0x00800000>;   /* HyperRAM */
-       };
-
        lbsc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -46,6 +41,33 @@
                        gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
                };
        };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x40000000 0x00800000>;   /* HyperRAM */
+       };
+};
+
+&ether0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&eth0_pins>;
+       status = "okay";
+       renesas,no-ether-link;
+       phy-handle = <&phy0>;
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&ether1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&eth1_pins>;
+       status = "okay";
+       renesas,no-ether-link;
+       phy-handle = <&phy1>;
+       phy1: ethernet-phy@1 {
+               reg = <0>;
+       };
 };
 
 /* EXTAL */
@@ -53,23 +75,16 @@
        clock-frequency = <24000000>;   /* 24MHz */
 };
 
-/* RTC_X1 */
-&rtc_x1_clk {
-       clock-frequency = <32768>;
+/* High resolution System tick timers */
+&ostm0 {
+       status = "okay";
 };
 
-/* USB_X1 */
-&usb_x1_clk {
-       clock-frequency = <48000000>;
+&ostm1 {
+       status = "okay";
 };
 
 &pinctrl {
-       /* Serial Console */
-       scif4_pins: serial4 {
-               pinmux = <RZA2_PINMUX(PORT9, 0, 4)>,    /* TxD4 */
-                        <RZA2_PINMUX(PORT9, 1, 4)>;    /* RxD4 */
-       };
-
        eth0_pins: eth0 {
                pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
                         <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
@@ -98,6 +113,12 @@
                         <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
        };
 
+       /* Serial Console */
+       scif4_pins: serial4 {
+               pinmux = <RZA2_PINMUX(PORT9, 0, 4)>,    /* TxD4 */
+                        <RZA2_PINMUX(PORT9, 1, 4)>;    /* RxD4 */
+       };
+
        sdhi0_pins: sdhi0 {
                pinmux = <RZA2_PINMUX(PORT5, 0, 3)>,    /* SD0_CD */
                         <RZA2_PINMUX(PORT5, 1, 3)>;    /* SD0_WP */
@@ -109,13 +130,9 @@
        };
 };
 
-/* High resolution System tick timers */
-&ostm0 {
-       status = "okay";
-};
-
-&ostm1 {
-       status = "okay";
+/* RTC_X1 */
+&rtc_x1_clk {
+       clock-frequency = <32768>;
 };
 
 /* Serial Console */
@@ -126,28 +143,6 @@
        status = "okay";
 };
 
-&ether0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&eth0_pins>;
-       status = "okay";
-       renesas,no-ether-link;
-       phy-handle = <&phy0>;
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-       };
-};
-
-&ether1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&eth1_pins>;
-       status = "okay";
-       renesas,no-ether-link;
-       phy-handle = <&phy1>;
-       phy1: ethernet-phy@1 {
-               reg = <0>;
-       };
-};
-
 &sdhi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&sdhi0_pins>;
@@ -161,3 +156,8 @@
        bus-width = <4>;
        status = "okay";
 };
+
+/* USB_X1 */
+&usb_x1_clk {
+       clock-frequency = <48000000>;
+};
-- 
1.9.1