Hi Wolfram,
On Thu, May 23, 2019 at 1:04 PM Wolfram Sang <[email protected]> wrote:
> On Thu, May 23, 2019 at 06:29:37PM +0900, Nguyen An Hoan wrote:
> > From: Hoan Nguyen An <[email protected]>
> >
> > Fix setting for bit WOVFE of RWTCSRA. Keep it enable follow hardware
> > document.
> > rwdt_write(priv, 0, RWTCSRB);
> >
> > while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
> > cpu_relax();
> > -
> > - rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
> > + /* Enable interrupt and timer */
> > + rwdt_write(priv, val | RWTCSRA_WOVFE | RWTCSRA_TME, RWTCSRA);
>
> What is the use of enabling an interrupt without having an interrupt
> handler?
Exactly.
> (And I never understood why there is an interrupt for an
> overflowing watchdog. We won't have time to serve it, or am I
> overlooking something obvious?)
I guess it (the hardware, not the Linux watchdog driver) might be used
as a generic timer? Or the interrupt may signal the RT core that the
application cores have been restarted?
But in the context of (the current) Linux watchdog driver, this doesn't
make much sense.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
