Hi Niklas-san,
> From: Niklas Söderlund, Sent: Tuesday, June 4, 2019 1:23 AM
>
> Hi Shimoda-san,
>
> Thanks for your work.
>
> On 2019-06-03 19:36:01 +0900, Yoshihiro Shimoda wrote:
> > According to the hardware manual of R-Car Gen2 and Gen3,
> > software should wait a few RLCK cycles as following:
> > - Delay 2 cycles before setting watchdog counter.
> > - Delay 3 cycles before disabling module clock.
> >
> > So, this patch adds such delays.
> >
> > Signed-off-by: Yoshihiro Shimoda <[email protected]>
> > Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> Small nit bellow, with or without that addressed.
>
> Reviewed-by: Niklas Söderlund <[email protected]>
Thank you for your review!
<snip>
> > +static void rwdt_wait(struct rwdt_priv *priv, unsigned int cycles)
> > +{
> > + unsigned long delays;
>
> Could this be unsigned int? It would still fit for a cycles number
> around 2000 and this change use 2 and 3 cycles.
I think so. I'll fix it on v3.
Best regards,
Yoshihiro Shimoda
