Bruce,

On Monday 03 September 2007 16:10, Bruce Ashfield wrote:
> On 9/3/07, Pradyumna Sampath <[EMAIL PROTECTED]> wrote:
> > Hi everyone,
> >
> > Here are some compile errors from the latest -rt patchset for powerpc
> > (mpc5200).
> >
> > arch/powerpc/kernel/entry_32.S: Assembler messages:
> > arch/powerpc/kernel/entry_32.S:231: Error: operand out of range
> > (0x00023d87 is not between 0x00000000 and 0x0000ffff)
> > arch/powerpc/kernel/entry_32.S:644: Error: operand out of range
> > (0x00022006 is not between 0x00000000 and 0x0000ffff)
> > arch/powerpc/kernel/entry_32.S:866: Error: operand out of range
> > (0x00020004 is not between 0x00000000 and 0x0000ffff)
> > arch/powerpc/kernel/entry_32.S:880: Error: operand out of range
> > (0x00020004 is not between 0x00000000 and 0x0000ffff)
> >
> > Im not sure whether this is the right thing to do but we got around
> > this by replacing the linux/include/asm-powerpc/thread_info.h with an
> > older version of the same file from 2.6.21-rt3.
>
> I don't have the code in front of me, but you can also shuffle
> the flags to make sure that macro being used in entry_32.S
> has all the flags within 16 bits (so the immediate operations
> will successfully assemble). That's the route I took. The flags
> have expanded past that threshold just recently.

Yes, there are 17 bits now. Can you provide a patch, how to handle 17 bits
now in arch/powerpc/kernel/entry_32.S? I haven't the experience to modify
the assembler code, so I have no idea how to change this line:

andi. 
r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)

without using an additional register (I don't know, what register I can use).
Can it look like this?

  lis 
r?,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)@h
  ori r?, r?, 
(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)@l
  and. r0, r9, r?

Regards,
Juergen
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