From: Maurus Cuelenaere <[email protected]> The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz. This patch adds support to the USB driver for setting the correct register bit according to the given clock.
This depends on the following patch: [PATCH] ARM: S3C64XX: Add USB external clock definition Signed-off-by: Maurus Cuelenaere <[email protected]> Signed-off-by: Ben Dooks <[email protected]> --- drivers/usb/gadget/s3c-hsotg.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 1f73b48..dce9366 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -23,6 +23,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/clk.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -2699,6 +2700,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg, */ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) { + struct clk *xusbxti; u32 osc; writel(0, S3C_PHYPWR); @@ -2706,6 +2708,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0; + xusbxti = clk_get(hsotg->dev, "xusbxti"); + if (xusbxti && !IS_ERR(xusbxti)) { + switch (clk_get_rate(xusbxti)) { + case 12000000: + osc |= S3C_PHYCLK_CLKSEL_12M; + break; + case 24000000: + osc |= S3C_PHYCLK_CLKSEL_24M; + break; + default: + case 48000000: + /* default reference clock */ + break; + } + clk_put(xusbxti); + } + writel(osc | 0x10, S3C_PHYCLK); /* issue a full set of resets to the otg and core */ -- 1.6.3.3 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
